Jeffery Winkler

NVFRAM's

	Imagine the year is 1980. You're typing the last stage of your term paper, the night 
before it's due. A thunderstorm brews on the horizon. Tense and tired, you have forgotten 
to save the document on your hard disk. Suddenly lightening strikes! Your computer goes 
down. Your term paper is lost. Wistfully, you long for the day when everything you write 
is automatically stored in a nonvolatile memory system as soon as you write and does not 
vanish if there's a power cut. Now fast-forward your mind to 2010, when all computers 
have NVFRAM's, or nonvolatile ferroelectric random-access memories - and read on!
	Studied for a century, ferroelectric materials belong to a class of crystals whose 
low symmetry engenders a spontaneous polarization along one or more crystal axes. The 
name "ferroelectric" is a misnomer since they contain no iron. The name derives from the 
fact that they are in some ways described mathematically in the same way as 
ferromagnetic materials. Ferroelectric crystals are characterized by having polarization 
vectors that can be oriented in two diametrically opposite directions, denoted by + and - 
,by applying an external magnetic field. The + and - polarization states in a ferroelectric 
crystal are due to displacements of positive metallic and negative oxygen ions in different 
directions.
	Let's say you have a NVFRAM where the unit cell is a cube, or a cubic perovskite, 
such as Pb(ZrTi)O3. If the Zr or Ti ion is in the up position, and the oxygen ions are in 
the down position, that counts as a "1". If you apply an electric field to it, it flips around 
so that the Zr or Ti ion is in the down position, and the oxygen ions are in the up position, 
and that counts as a "0". These cubic memory cells are arranged in a square matrix. A 1-
magabit memory will therefore have 1000 rows and 1000 columns. To overcome the 
"crosstalk" problem that beset early NVFRAM architecture, each memory cell capacitor 
is isolated from its neighbors by means of a passgate transistor. The way you change the 
bit within a cell is by applying 50% of the voltage needed to switch the polarization along 
a specific row, known as the bit line, and 50% of the needed voltage along the correct 
column, known as the word line. Only at the preselected cell will the two pulses add up 
to a voltage necessary to switch the polarization state.
	Destructive and nondestructive reading schemes are being explored, although it 
appears that the first generation of NVFRAM's will be based on a destructive reading 
scheme. In this approach, the bit is read when a positive switching voltage is applied to a 
memory cell in the same way as the writing voltage described above. If the cell 
polarization is already +, representing 1, then only a linear nonswitching response is 
measured, in the form of a voltage across a 10 - 15 ohm resistor. If the cell is -, a 
switching response greater than the linear response is measured because it contains the 
additional displacement current term dP/dt, where P is the polarization. A sense amplifier 
then compares this response with that of a reference cell, which is always polarized +. 
Thus the logic state 1 or 0 is read, and in a destructive reading scheme, the memory cell 
reverts to the original 1 or 0 that was stored in the cell before the information was read.
	The fact that ferroelectric layers can maintain an induced polarization, even in the 
absence of a voltage, provides the unique nonvolatility of NVFRAM's. Future personal 
computers based on NVFRAM's will not require backup disk memories. It is likely, 
therefore, that they will have no moving parts and be far smaller that today's PC's. 
Current fast-operating random access memories (DRAM's) could be replaced with 
NVFRAM's.
	NVFRAM's should also increase speed. In a random access memory, the ultimate 
performance speed is limited not by access time but by the interconnect time taken by the 
current from one transistor to charge the gate of the next. Since the 600 ps charging time 
for ferroelectric capacitors is already near the interconnect time, switching does not 
intrinsically limit device speed. The size of the memory system should also decrease. 
Functioning ferroelectric layers thinner than 0.9 nm have been produced in the 
laboratory.
	Now that the primary source for funding for this field has shifted from 
government to industry, several memory manufactors are currently in the race to bring 
NVFRAM's to market. Materials integration strategies already developed are being 
implemented to embed 64-kilobit ferroelectric memories in microchip controllers.